1. Field of the Invention
The present invention generally relates to integrated circuit contact structures and, in particular, to a method for forming conductive, or semiconductive, contact plugs for fully planarized integrated circuit devices, particularly those fabricated using complementary metal-oxide-semiconductor (CMOS) processes.
2. Description of the Related Art
The advent of very large scale integrated (VLSI) circuitry in the semiconductor field has created many problems, including the need to effectively interconnect the tens, and even hundreds, of thousands of active components often present on a VLSI circuit die. The standard interconnection mechanism in the current state of the art is basically a patterned thin film of conductive material, e.g., aluminum, deposited upon an insulator layer which has holes (aka contact windows) leading down to the junction region of each active device to be coupled.
In VLSI, the horizontal dimension for component regions on the surface of the wafer is approaching the 1 micron range. Yet, the vertical height, or depth, of contact apertures may not be amenable to this scaling because of constraints such as parasitic capacitance and metal interconnect step coverage. These relatively deep contact holes are not amenable to sputtered metal films used for interconnection. Poor step coverage results in losses in yield and reliability.
One method used to combat this difficulty is to use etching methods which form contact apertures with sloping sidewalls. This can often solve the problem of poor metal step coverage into the contact windows. However, this method does not help achieve shrinkage because the dimension at the top of the contact window remains relatively large.
Current CMOS integrated circuits have contacts to p+ and n+ diffused regions placed well inside of the diffusion area in order to prevent the contact hole from opening over both the p+ or n+ region and the surrounding field isolation region (which would result in an electrical short between the junction and the field, rendering the circuit inoperative). The spacing requirements for aligning the apertures well within the diffusion region is also contrary to the goal of scaling.
A related problem occurs in both NMOS and CMOS VLSI because of the very shallow n+ and p+ junctions commonly used. When contacted directly by metal interconnection layers, such as aluminum or aluminum/1% silicon material, "spiking" of the metal through the junction can occur. This also results in losses in yield and reliability.